Double-extension formation using offset spacer

ABSTRACT

A MOS transistor structure is disclosed. A gate electrode is disposed on a semiconductor substrate. A first extension of a predetermined impurity type is substantially aligned with the gate electrode in the substrate. A second extension of the predetermined impurity type overlaps with the first extension in the substrate. The first extension has at least one lateral boundary line closer to the gate electrode than that of the second extension. Source and drain regions of the predetermined polarity type overlaps with the first and second extensions in the substrate. The second extension has at least one lateral boundary line closer to the gate electrode than that of the source and drain regions. The source and drain regions are deeper than the second extension, which is deeper than the first extension, so that they collectively reduce lateral abruptness of the source and drain, while maintaining a reduced extension resistance.

BACKGROUND

The present invention relates generally to semiconductor devices, andmore particularly to a method for implanting multiple extensions on ametal oxide semiconductor field effect transistor.

A MOSFET typically has three or four terminals. A three-terminal MOSFETincludes a source, a drain, and a gate. A voltage applied to the gateterminal controls MOSFET channel resistance. The gate region, which isnot a junction, is a metal oxide “sandwich” running the length of thechannel surface. On the other hand, MOSFET source and drain regions arejunctions and not simply contacts.

Taking an n-channel MOSFET for example, the source and drain are shallown-type regions in an n-channel MOSFET. The gate material, such aspolycrystalline silicon, is typically placed over a channel, butseparated from the channel by a thin layer of insulating silicondioxide. The channel is of a p-type material. With no bias voltageapplied to the gate, the resistance of the path between the source anddrain is high, and there will be no current flowing between the tworegions. When an appropriate voltage is applied between the gate andsource terminals, the electric field generated penetrates through theoxide and creates a so-called “inversion channel” in the channelunderneath. Since the inversion channel is of the same type, i.e. P-typeor N-type, as the source and drain, it provides a conduit (or the“channel”) through which current can pass. By varying the voltagebetween the gate and body, conductivity can be modulated.

Semiconductor device fabrication is a multiple-step sequence to createchips used in everyday electrical and electronic devices. Fabrication ofa MOSFET normally includes a silicon substrate wafer as a starting base.A gate oxide is grown and polycrystalline silicon is added to create agate. Light pattern is projected to photoresist and a chemical washesaway material that is illuminated or shaded from the stencil dependingon positive or negative exposure; this process is called developing. Ionimplantation deposits N-type or P-type material to create a source anddrain. Additionally the process can include many other steps such asphosphorus diffusion, annealing, and deposition of material to give theMOSFET a unique bias, resistive characteristics and properties.

However, conventional fabrication methods produce MOSFETs having notonly a high resistance between the source, drain and diffusion channel,but also geometry issues in depth or spread related to diffusion duringannealing. Furthermore, control issues may also be problematic.

As such, desirable in the art of semiconductor designs are additionalMOSFET fabrication methods that provide more robust, more configurableMOSFETs.

SUMMARY

In view of the foregoing, the following provides a method to enhance thesource and drain layer resistance by using multiple lightly-dopedextensions on the source and drain, and by making part of theheavily-doped extensions deep enough to provide more input and outputconductivity.

In various embodiments, a MOS transistor structure is disclosed. A gateelectrode is disposed on a semiconductor substrate. A first extension ofa predetermined impurity type is substantially aligned with the gateelectrode in the substrate. A second extension of the predeterminedimpurity type overlaps with the first extension in the substrate. Thefirst extension has at least one lateral boundary line closer to thegate electrode than that of the second extension. Source and drainregions of the predetermined polarity type overlaps with the first andsecond extensions in the substrate. The second extension has at leastone lateral boundary line closer to the gate electrode than that of thesource and drain regions. The source and drain regions are deeper thanthe second extension, which is deeper than the first extension, so thatthey collectively reduce lateral abruptness of the source and drain,while maintaining a reduced extension resistance.

The construction and method of operation of the invention, however,together with additional objectives and advantages thereof will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 presents a cross sectional area of a conventional MOSFETstructure.

FIGS. 2A-2C present a series of steps illustrating a method forconstructing a MOSFET structure in accordance with the first embodimentof the present invention.

FIGS. 3A-3C present a series of steps illustrating a method forconstructing a MOSFET structure in accordance with the second embodimentof the present invention.

DESCRIPTION

The present disclosure provides methods for form double extension toimprove the performance of transistors which will have less input andoutput resistance and a smoother source and drain layer transition. Thefollowing provides a detailed description of two methods for fabricatingan improved MOSFET structure.

FIG. 1 presents a cross sectional area of a conventional N-MOSFETstructure 100. Basic fabrication of such a conventional N-MOSFETstructure 100 starts with a semiconductor substrate 102. The substrate102 is doped with special impurities to form a P-type material. An oxidelayer 104 is then formed on the substrate 102. A layer of gate materialsuch as the polycrystalline silicon (poly) 106 is then deposited overthe oxide layer 104. A photoresist coating (not shown) is typicallyapplied to the substrate 102. After the substrate 102 is exposed to alight pattern, the photoresist coating wafer is developed. The exposedareas are dissolved if positive photoresist is used. A portion of thepoly 106 is then etched, followed by the oxide layer 104. The abovesteps provide an “island” comprising the oxide layer 104 and the poly106, which constitutes the N-MOSFET's gate electrode.

A source 108 and a drain 110 of the N-MOSFET are created by adding alightly doped N-type material to the substrate 102 through implantation,which is typically performed by using an atomic accelerator. Theimplantation process deposits material near the surface and in a uniformprocess. The process also slightly damages the substrate 102. To fix thedamage, the wafer is annealed, or heat treated, in order to modify thematerial's properties. However, a side effect of the annealing processis diffusion, which is caused by the natural migration of atoms from amore concentrated region to a less concentrated region. Generally,lateral diffusion is undesirable, however sometimes unavoidable, insemiconductor device fabrication as it causes lateral distortion of thedevice geometry and can create shorts or parasitic capacitance. A length112 illustrates diffusion of the implanted material. The small overlapof length 112 of the N-type material and the poly 106 form a parasiticcapacitance that changes the transistor's speed properties.

In semiconductor fabrication, the addition of layers of materialsnormally creates a parasitic capacitance between layers. This parasiticcapacitance typically works against the design because it causes thetransistor to turn on slowly as the parasitic capacitance charges up. Away to minimize parasitic capacitance resulting from lateral diffusionis to use various oxide offset spacers 114 which can be added to thevertical sides of the gate as an option, prior to a specific implant.

The half-completed transistor is then covered with an oxide material.The oxide is chemically etched away in such a way that only sidewallspacers 116 remain. This sidewall spacer 116 is used as a mask foradditional selective implantations. Finally, a heavily doped N-typematerial is implanted and diffused to the substrate 102 to create a deepextension 118 at the source 108 and the drain 110.

The above steps explain the basic steps for making an N-MOSFET. Variousways of manufacturing a MOSFET exist and each depends on the desiredproperties of the transistor needed. A clear disadvantage from thisconventional method is the lateral abruptness degradation with anincreasing length 120. The surface area and volume taken by thelightly-doped material is not sufficient in many cases to form a goodconductive medium for a required current density. This is due to a poortransition of the resistive properties of the materials used.Additionally, a depth 122 at any given length 112 may not be sufficientfor the current flow when the gate is turned on. Another disadvantage isthat the ratio between depth 122 and the length 120 ratio remainsstatic. In addition, several annealing processes might encourage lateraldiffusion along with vertical diffusion.

FIGS. 2A-2C present steps 202, 214 and 224 illustrating a method forconstructing a MOSFET structure in accordance with the first embodimentof the present invention. In this embodiment, the MOSFET structureincludes multiple lightly-doped extensions and one heavily-dopedextension. In step 202, a semiconductor substrate 204 is doped with aP-type material after a gate structure is formed on the substrate 204. Agate having an oxide layer 206 and a poly 208 is fabricated by processessimilar to those described in the fabrication of the N-MOSFET structure100. The thickness of the oxide layer 206 can be between 0-20 angstroms.A first extension 210 is formed by implanting selected impurities to thesubstrate 204 as it is “masked” by the gate to create impurity regionswhich are the bases for the source and drain. This first extension 210is lightly-doped with an N-type impurity material such as arsenic (As),and is relatively shallow in its depth. This can be done by a low energysource such as 5 KeV for As and BF₂, and <2 KeV for Boron, which is aP-type impurity material. The doping impurity dosage may be in a rangebetween 5e13 and 1e16 cm-2. The first extension 210 is roughly alignedwith the edges of the gate. In order to increase a dopant concentrationin a localized area, a rapid heat treatment known as annealing isusually processed. Alternatively, this annealing process can be avoidedand the desired dopant concentration can still be achieved, depending onthe temperature during formation of a subsequent spacer is a laterstage. After annealing, a portion of this first extension 210 extendsboth vertically and laterally. Laterally, it now extends beyond theedges of the gate and further underneath the gate. Vertically, the firstextension region now has a bigger depth. This two-dimensional extensionis caused by diffusion, thereby creating a high concentration extension212. It is understood that for illustration purposes, only the extension210 is illustrated on the left side of the gate, and only the extension212 illustrated on the right side of the gate, but in fact, after theannealing, the extension on the left side should look like the extension212.

In step 214, oxide offset spacers 216 are added to the verticalsidewalls of the gate, which have a width ranging from 50 to 400angstroms. The oxide offset spacers 216 function as a mask for placing asecond extension 218. The second extension 218 of the same type (i.e.,using the same type of impurities) is implanted and further diffusedthrough a heating process. This time, the depth of the second extensionis deeper than the first extension. This depth is an important factorthat affects the resistance of the source and drain. This secondextension overlapping the first extension creates a gradual increase inconductivity to the increasing geometric depth and the concentrationcreated by extensions 218 and 220. The extension 220 diffuses under theoxide offset spacers 216, thereby minimizing a parasitic capacitancefrom being created.

In step 224, the top surface of the transistor-in-process is coveredwith an oxide. The oxide is etched in such a way where only sidewallspacers 226 remain. Like the oxide offset spacers, the sidewall spacers226 are formed to function as a mask to self align the source and drainregions 228. The source and drain 228 are implanted and diffused througha heating process. The source and drain are heavily doped with an N-typeimpurity material. As it is seen, from the first extension to the thirdextension, each succeeded extension is implanted at a higher energy inorder to create a deeper layer.

Advantages of using this fabrication technique arise from the gradualgeometric size and impurity material concentration of the extensions,from small to large. This process benefits from rapid thermal processesor the use of high temperature sub-melt laser annealing which cancontribute to diffusion-less profiles. Additionally, the fabrication ofa transistor with a minimal diffusion distance 230 caused by lateraldiffusion and an increase in an extension depth 232 can substantiallyreduce input and output resistance related to the source and the drain.It is understood that the abruptness of the extension of the source anddrain is measured by the lateral diffusion distance 230. As it can beseen on the drawings, the overlapping area between the first and secondextension that extends out and underneath the gate structure and thespacers provides a “two-step” decline in depth instead of one step as inthe conventional practice. It is said that the two-step decline reducesthe overall abruptness of the extension.

FIGS. 3A-3C present steps 302, 316, and 324 illustrating a method forconstructing a MOSFET structure in accordance with the second embodimentof the present invention. In this embodiment, the MOSFET structureincludes multiple lightly-doped extensions and a heavily-dopedextension. In step 302, a semiconductor substrate 304 is doped with aP-type material. The gate includes an oxide layer 306 and a poly 308,which are fabricated using similar processes as described in thefabrication of the N-MOSFET structure 100. The sidewalls of the gate arefirst covered with an oxide to create thick offset spacers 310. A firstlayer 312 of N-type impurity material is implanted to the substrate 304to create the base for the extension. The wafer is then annealed and aportion of the first layer 312 diffuses slightly to form a firstextension 314. The edges of the first extension 314 are substantiallyaligned with the spacers 310.

In step 316, the oxide offset spacers 310 are thinned by etching,thereby forming thinned spacers 318, which have widths narrower thanthose of the original “thick” spacers 310. The thinned spacers 318 isintended to help align a shallow implantation of impurities. The etchingprocess creates a new shadow line, as depicted at a corner 320 betweenthe edge of the oxide offset spacer 318 and the surface of the substrate304 that will become the implant edge for the next extension. A thinlayer of lightly-doped N-type impurity material is then implanted anddiffused, thereby creating a thin extension 322. At this point, theextension for the source and drain is appropriately formed by theoverlapping first and second extension, both formed by having the sametype of impurities. As it can be seen from FIG. 3B, the abruptness ofthe edges underneath the gate is reduced due to the separate engineeringof the first and second extensions. Like the one depicted in FIGS.2A-2C, a two-step decline has been formed.

In step 324, the surface of the transistor is covered with an oxide. Theoxide is etched in such a way where only sidewall spacers 326 remain.The source and drain 328 are then implanted and diffused. The source anddrain 328 includes a heavily-doped N-type material. The source and drainare implanted at a higher energy in order to create a deeper layer.

The need to implant the thin extension 322 only after implanting thefirst extension 314 is due to a concern with the thermal budget, or theexposure to fabrication heat cycles. This method can reduce transientenhanced diffusion or damage caused to the crystal during diffusionunder the high energies of implantation. The reduction in exposurereduces diffusion of dopant in the source and drain 328, as well as thegradual diffusion of the source and drain layers due to annealing intothe inversion channel area, which can cause a punch through if “smeared”long enough.

In various embodiments, the fabrication method specifically mentionsN-MOSFET. While examples are given for N-MOSFET, it is understood bythose skilled in the art that a P-MOSFET can also be fabricated usingthe same methods. Moreover, while only the basic steps to MOSFETfabrication are illustrated, additional steps are contemplated forchanging a MOSFET's properties to match a given design requirement.

This invention proposes a novel method that uses multiple extensions ofdifferent geometries and concentrations. The transistor created by thepresent invention provides an (source/drain) extension profile that hasa minimum lateral diffusion, while achieving minimal extensionresistance by having deep vertical diffusion. Advantages of theinvention include less diffusion with special low heat anneal processesand deeper source and drain geometries at the outer extremities, therebyleading to more conductivity or less resistance. Multiple extensions maybe essential to achieve both short channel control and low extensionresistance and thus high drive current.

The above illustration provides many different embodiments orembodiments for implementing different features of the invention.Specific embodiments of components and processes are described to helpclarify the invention. These are, of course, merely embodiments and arenot intended to limit the invention from that described in the claims.

Although the invention is illustrated and described herein as embodiedin one or more specific examples, it is nevertheless not intended to belimited to the details shown, since various modifications and structuralchanges may be made therein without departing from the spirit of theinvention and within the scope and range of equivalents of the claims.Accordingly, it is appropriate that the appended claims be construedbroadly and in a manner consistent with the scope of the invention, asset forth in the following claims.

1. A method for constructing a metal-oxide-semiconductor field effecttransistor (MOSFET) structure with multiple doped source/drainextensions, the method comprising: forming a gate electrode on asemiconductor substrate; forming a first extension of a predeterminedimpurity type substantially aligned with the gate electrode in thesubstrate; forming one or more first set of spacers on sidewalls of thegate electrode; forming a second extension of the predetermined impuritytype substantially aligned with the first set of spacers and overlappingwith the first extension in the substrate; forming one or more secondset of spacers laterally onto the first set of spacers; and formingsource and drain regions of the predetermined impurity type overlappingwith the first and second extensions and substantially aligned with thesecond set of spacers in the substrate, wherein the first set of spacershelp to align the first and second extensions so that they collectivelyreduce lateral abruptness of the source and drain, while maintaining areduced extension resistance.
 2. The method of claim 1 wherein the firstextension is shallower than the second extension.
 3. The method of claim2 wherein the first extension has at least one lateral boundary linecloser to the gate electrode than that of the second extension.
 4. Themethod of claim 3 wherein the second extension has an impurityconcentration no smaller than that of the first extension.
 5. The methodof claim 4 wherein the impurity concentration of the first extensionapproximately ranges from 5e13 to 1e16 cm-2.
 6. The method of claim 4wherein the impurity concentration of the second extension approximatelyranges from 1e14 to 1e16 cm-2.
 7. The method of claim 1 wherein thefirst extension is formed using the gate electrode for alignment.
 8. Themethod of claim 1 wherein the second extension is formed using the firstset of spacers for alignment.
 9. The method of claim 1 wherein the firstextension controllably defines a lateral diffusion distance underneaththe gate electrode.
 10. A metal-oxide-semiconductor field effecttransistor (MOSFET) structure with multiple doped source/drainextensions, comprising: a gate electrode disposed on a semiconductorsubstrate; a first extension of a predetermined impurity typesubstantially aligned with the gate electrode in the substrate; a secondextension of the predetermined impurity type overlapping with the firstextension in the substrate, the first extension having at least onelateral boundary line closer to the gate electrode than that of thesecond extension; source and drain regions of the predetermined polaritytype overlapping with the first and second extensions in the substrate,the second extension having at least one lateral boundary line closer tothe gate electrode than that of the source and drain regions, whereinthe source and drain regions are deeper than the second extension, whichis deeper than the first extension, so that they collectively reducelateral abruptness of the source and drain, while maintaining a reducedextension resistance.
 11. The MOSFET structure of claim 10 wherein thesecond extension has a predetermined impurity concentration no smallerthan that of the first extension.
 12. The MOSFET structure of claim 11wherein the predetermined impurity concentration of the first extensionapproximately ranges from 5e13 to 1e16 cm-2.
 13. The MOSFET structure ofclaim 11 wherein the predetermined impurity concentration of the secondextension approximately ranges from 1e14 to 1e16 cm-2.
 14. The MOSFETstructure of claim 10 further comprising one or more first set ofspacers on the side walls of the gate electrode.
 15. The MOSFETstructure of claim 16 further comprising one or more second set ofspacers laterally formed onto the first set of spacers.
 16. A method forconstructing a metal-oxide-semiconductor field effect transistor(MOSFET) structure with multiple doped source/drain extensions, themethod comprising: forming a gate electrode on a semiconductorsubstrate; forming one or more first set of spacers on sidewalls of thegate electrode; forming a first extension of a predetermined impuritytype substantially aligned with the first set of spacers in thesubstrate; thinning the first set of spacers; forming a second extensionof the predetermined impurity type substantially aligned with the firstset of thinned spacers and overlapping with the first extension in thesubstrate; forming one or more second set of spacers laterally onto thefirst set of spacers; and forming source and drain regions of thepredetermined impurity type overlapping with the first and secondextensions and substantially aligned with the second set of spacers inthe substrate, wherein the first set of spacers help to align the firstand second extensions so that they collectively reduce lateralabruptness of the source and drain, while maintaining a reducedextension resistance.
 17. The method of claim 16 wherein the secondextension is shallower than the first extension.
 18. The method of claim17 wherein the second extension has at least one lateral boundary linecloser to the gate electrode than that of the first extension.
 19. Themethod of claim 16 wherein the second extension has a predeterminedimpurity concentration approximately ranging from 5e13 to 1e16 cm-2. 20.The method of claim 16 wherein the first extension has a predeterminedimpurity concentration approximately ranging from 1e14 to 1e16 cm-2.